|BITSCOPE||design||hardware||convertor||40 Mhz option|
The new ADC module gives you the option of sampling data at 40 MHz.
Bitscope is normally configured to drive the ADC at 25 MHz and must be modified to run at 40 MHz. However, before you leap in and do this, you may wish to consider some of the trade-offs.
Aperiodic Waveform Capture
If the signals you are interested in are periodic, then sub-sampling allows you to measure frequencies beyond 70 MHz running the ADC at only 25 MHz. Indeed, for reasons described below it is preferable to run the ADC at this lower rate.
However, if you wish to capture aperiodic waveforms or one-shot events, and the frequency content of these signals is greater than 12 MHz (ie, half the 25 MHz sample rate), then running the ADC at 40 MHz will allow you to see frequency components up to 20 MHz.
The ADC5540 converter performance varies with sample clock frequency. A close look at the data sheet shows that the ADC begins to lose ENB (effective number bits) when clocked at its maximum rate. This shows up as nonlinearity (noise) imposed on the signal which increases with input frequency.
Some real-world examples demonstrate the difference...
Another issue is sample memory usage. A 40 MS/s Bitscope will consume sample RAM twice as fast and limit the maximum capture to about half. Alternatively, if you normally capture less than a full buffer of data, running at 40 MS/s means you will generate up to 2 times as much data which will slow the serial link upload time.
If you plan to use Bitscope as a high speed logic analyzer with simultaneous analogue signal capture, you may want to run the clock at 40 MHz. This will allow you to capture logic transitions at almost twice the speed of the standard Bitscope.
Modifying Bitscope for 40 MS/s
Bitscope is capable of being clocked at up to 50MS/s limited by the PLD, SRAM, and the PIC microcontroller. The 40 MS/s limit described here is due to the ADC module, and the standard 80 MHz PLD and 15 ns SRAM components. If you are not interested in analogue data capture (ie, you're not using an ADC), you can in fact clock Bitscope at 50 MS/s for use as a very high speed logic analyzer if you use a 100 MHz PLD, 12 ns SRAM and omit the ADC.
To run Bitscope at 40 MS/s you have two choices; either install an 80 MHz OSC module to replace the standard 50 MHz part, or enable the clock doubler circuit and use a 40 MHz OSC module.
The following notes detail a board level modification to Bitscope which should only be attempted by an experienced person. Desoldering components from a multilayer card must be done carefully with appropriate tools to avoid damaging the PCB.
How the clock doubler works
Normally, Bitscope uses a x2 Oscillator module with a synchronizing flip-flop to generate zz-clk (the sample clock). To allow more commonly available OSC modules to be used at sample rates of 40MHz (80MHz OSC), a simple clock doubler circuit is included in the Bitscope design. This circuit is normally disabled, but can be activated by adding an RC filter.
Refering to the schematic above:
The XOR timing diagram below shows how a x2 clock is generated.